Vol. 2 No. 5 (2016)

Published: 2016-10-29

Articles

Design and Implementation of MUX Based FIR filter with Hybrid Adder

U.PRAVEEN KUMAR1, W.YASMEEN 2
- FULLTEXT PDF
DESIGN AND IMPLEMENTATION OF SEQUENTIAL AND PARALLEL MICROPROGRAMMED FIR FILTER

S.Sravanthi1, K.Naga Koushil Reddy 2
- FULLTEXT PDF
Implementation of SHA-2(256) & SHA-3(512) Algorithms for Information Security

M.Mounika1, T.Thammi Reddy 2
- FULLTEXT PDF
Quad-Fault Tolerant Architecture Design for Ripple Carry Adder

Vayalasetti Swarnalatha1, Praveen Kumar Polisetty 2
- FULLTEXT PDF
Design of floating point multiplier using karatsuba - urdhava multiplier and koggestone adder

U.Sudharani 1, K.Siva Sundari 2
- FULLTEXT PDF
DESIGN AND IMPLEMENTATION OF RECONFIGURABLE 64-POINT DISCRETE COSINE TRANSFORM (DCT) ARCHITECTURE

Meesala Shiva Kumar 1, Dr. G V Maha Lakshmi 2
- FULLTEXT PDF
Design of SPI Bus Protocol with Built-In-Self-Test using CA

GANTI PRAVEEN ANAND 1, N.LATHA 2
- FULLTEXT PDF
EFFICIENT SCALABLE FIR FILTER IMPLEMENTATION USING VEDIC MULTIPLIERS

Chunduri Krishna Chaitanya1, K V S Sri Harsha2
- FULLTEXT PDF
FPGA Implementation of 16 bit MUX Based Multiplier

Jaganmohan 1, K.RAMBABU 2
- FULLTEXT PDF
Design and Implementation of Area Efficient S-Box using Combinational logic with Pipelined AES

G.Hymavathi 1, V.Venkanna 2
- FULLTEXT PDF
Design and Implementation of Convolution and Deconvolution by using Sutras

Allakonda VamshiKrishna1, A Karthik2, Dr K Srinivasulu3
- FULLTEXT PDF
Design of radix 2 and radix4 multipliers with BIST

A.SREENU NAIK 1, YELGAMONI RAVINDER 2
- FULLTEXT PDF
FPGA Realization of MUX Based FIR Filter Architecture

K.Sabitha 1, S.Sreehari 2
- FULLTEXT PDF
DESIGN OF 64 bit MAC UNIT WITH VEDIC MULTIPLIER AND REVERSIBLE DKG GATE

K.RAVI 1, MADARAPU AJITHRAO 2
- FULLTEXT PDF
Design and implementation of Floating point multiplication with Karatsuba-Urdhva multiplier and kogge stone adder

DONURU MADHAVI 1, V.VENKANNA 2
- FULLTEXT PDF
Design and Implementation of Sequential and Parallel FIR Filters using Vedic Multiplier with Compressors

APPAM TEJASWI 1, MADARAPU AJITHRAO 2
- FULLTEXT PDF
DESIGN OF EFFICIENT RECONFIGURABLE INTERPOLATION FILTER

V. Rajendra chary 1, C. Pamuleti 2
- FULLTEXT PDF
Design of 64-Bit Vedic Multiplier and Square Architectures

Kriti Rashmi Sinha 1, Pathloth Krishnamurthy 2
- FULLTEXT PDF
Design and Implementation of radix Booth Multiplier with BIST TPG

K.Rajani 1, Prof.I.Venugopal 2
- FULLTEXT PDF
FPGA Implementation of Vedic ALU with Application Specific Reversible Gates

Marri Vasudha 1, V.Suresh Kumar 2
- FULLTEXT PDF
Design of Reconfigurable Architecture for 64-point DCT

M.PHANINDRA BABU 1, MADARAPU AJITHRAO 2
- FULLTEXT PDF
Design of Memory controller with AXI Bus interface

1 K.KRISHNAIAH, 2 YELGAMONI RAVINDER
- FULLTEXT PDF
DESIGN OF AREA EFFICIENT AND POWER OPTIMIZED CARRY SELECT ADDER

Deepak Kumar1, Pathloth Krishnamurthy2
- FULLTEXT PDF
Design of Area Efficient Substitution-Box with Pipelined AES

K.Keerthi Sucharitha 1, G. Hamarnath 2, T.Chakrapani3
- FULLTEXT PDF
RF Front-end Design of a Digital TV Receiver

D. Sony Dr.G.V. Mahalakshmi
- FULLTEXT PDF

Vol. 2 No. 5 (2016)

Articles

Design and Implementation of MUX Based FIR filter with Hybrid Adder

DESIGN AND IMPLEMENTATION OF SEQUENTIAL AND PARALLEL MICROPROGRAMMED FIR FILTER

Implementation of SHA-2(256) & SHA-3(512) Algorithms for Information Security

Quad-Fault Tolerant Architecture Design for Ripple Carry Adder

Design of floating point multiplier using karatsuba - urdhava multiplier and koggestone adder

DESIGN AND IMPLEMENTATION OF RECONFIGURABLE 64-POINT DISCRETE COSINE TRANSFORM (DCT) ARCHITECTURE

Design of SPI Bus Protocol with Built-In-Self-Test using CA

EFFICIENT SCALABLE FIR FILTER IMPLEMENTATION USING VEDIC MULTIPLIERS

FPGA Implementation of 16 bit MUX Based Multiplier

Design and Implementation of Area Efficient S-Box using Combinational logic with Pipelined AES

Design and Implementation of Convolution and Deconvolution by using Sutras

Design of radix 2 and radix4 multipliers with BIST

FPGA Realization of MUX Based FIR Filter Architecture

DESIGN OF 64 bit MAC UNIT WITH VEDIC MULTIPLIER AND REVERSIBLE DKG GATE

Design and implementation of Floating point multiplication with Karatsuba-Urdhva multiplier and kogge stone adder

Design and Implementation of Sequential and Parallel FIR Filters using Vedic Multiplier with Compressors

DESIGN OF EFFICIENT RECONFIGURABLE INTERPOLATION FILTER

Design of 64-Bit Vedic Multiplier and Square Architectures

Design and Implementation of radix Booth Multiplier with BIST TPG

FPGA Implementation of Vedic ALU with Application Specific Reversible Gates

Design of Reconfigurable Architecture for 64-point DCT

Design of Memory controller with AXI Bus interface

DESIGN OF AREA EFFICIENT AND POWER OPTIMIZED CARRY SELECT ADDER

Design of Area Efficient Substitution-Box with Pipelined AES

RF Front-end Design of a Digital TV Receiver

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