EFFICIENT SCALABLE FIR FILTER IMPLEMENTATION USING VEDIC MULTIPLIERS
The micro architecture of digital FIR filter consists of a data path and a control unit. The data path is the computational engine of FIR filter and mainly consists of adders, multipliers and delay elements. The hardware implementation of a Sequential and parallel digital FIR filter architecture using a novel micro programmed controller is presented. The main advantage of the micro programmed controller is its flexibility in modifying the micro program stored in ROM based control memory. To improve the performance of FIR filter, an efficient multiplier is required. Wallace tree and Vedic multipliers are used for the implementation of sequential and parallel micro programmed FIR filter architectures we have proposed a novel high speed and area efficient Vedic multiplier using compressors is used for the implementation of sequential and parallel micro programmed FIR filter architectures. The proposed technique, a 4-tap sequential and parallel FIR filter is implemented using Xilinx Spartan 3e FPGA. The proposed FIR filter is coded in VERILOG. The design can be easily modified to implement higher-order and high speed FIR filters which are commonly used in video and image processing applications.
How to Cite
International Journal of Engineering Science and Generic Research (IJESAR) by Articles is licensed under a Creative Commons Attribution 4.0 International License.