DESIGN OF EFFICIENT RECONFIGURABLE INTERPOLATION FILTER

Abstract

An Interpolation filter with filter length, N=16 and up-sampling factors 2, 4 and 8 is developed in this paper. The Vector Generation Unit and Arithmetic Unit, which are the major blocks of the proposed architecture is developed by writing Verilog code. Another block Coefficient Selection Unit is developed using multiplexer-based design. A novel block-formulation is presented to share the partial results for parallel computation of filter outputs of different up-sampling factors. In this architecture, the partial results are made to reuse in the Arithmetic unit of the proposed method by which computational complexity reduces. Further, the filter length is increased to 32 and similar analysis is done by using up-sampling factors 2, 4, 8 and 16. Unlike the existing methods, all the blocks are developed using single software. All synthesis and simulation reports are observed using Xilinx 14.2 ISE. KEYWORDS: Arithmetic unit, Interpolation filter, vector generation unit, up-sampling factor.