FPGA Implementation of Vedic ALU with Application Specific Reversible Gates
The Urdhva Triyambakam method derived from the ancient Indian mathematics will be used in the proposed project. Reversible circuits, on the other hand, reduces the power dissipation incurred due information/bits loss as in the case of an irreversible circuit making way for better power utilization . The proposed ALU design has a four bit control signal. It performs six arithmetic operations and ten logical operations. The proposed ALU uses both reversible and semi reversible gates in it. Arithmetic operations are addition, subtraction, multiplication, division, increment and decrement. Logical operations are and gate, or gate, not gate, nand gate, nor gate, xor gate, xnor gate, a’b, barrel left shifter, barrel right shifter. The operations performed based on the control bits are as follows. Total of sixteen operations are performed by the proposed ALU. The proposed ALU is coded in Verilog followed by synthesization using XilinxISE13.2i.
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