FPGA Realization of MUX Based FIR Filter Architecture

Authors

  • K.Sabitha 1, S.Sreehari 2 1 PG Scholar, Department of ECE, MVSR Engineering College, Hyderabad, India kondamsabitha@gmail.com 2 Assistant Professor, Department of ECE, MVSR Engineering College, Hyderabad, India

Abstract

In digital filter implementation, the multiplier usage is avoided by using MUX based multiplier and Look up Table (LUT) based multiplier. Odd multiple storage proposed by stores the product of odd multiple of co-efficient and the input. The advantage of storing odd multiple is that even multiples can be obtained by a simple left shift operation.MUX based multiplication is carried out only with MUX and shifters and CSLA BEC adder. Proposed MUX based multiplication is carried out only with MUX and shifters and CSLA DLATCH adder. Proposed MUX based CSLA DLATCH adder increases the speed over MUX based CSLA BEC. The designs’ve been implemented using Verilog and synthesized using Xilinx 13.2 Spartan 3e kit. Keywords: FIR filter, Look-up Table, Reconfigurable Architecture, and Distributed Arithmetic.

Downloads

Published

2016-10-30

How to Cite

2, K. 1, S. (2016). FPGA Realization of MUX Based FIR Filter Architecture. International Journal of Engineering Science and Generic Research, 2(5). Retrieved from https://ijesar.in/index.php/ijesar/article/view/48

Issue

Section

Articles