DESIGN OF AREA EFFICIENT AND POWER OPTIMIZED CARRY SELECT ADDER

Authors

  • Deepak Kumar1, Pathloth Krishnamurthy2 1 PG Scholar, Department of ECE, Brilliant Institute of Engineering and Technology, Hyderabad, India 2 Assistant Professor, Department of ECE, Brilliant Institute of Engineering and Technology, Hyderabad, India

Abstract

To study the data dependence and to identify redundant logic operations, we are analysing logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA. A new logic formulation for CSLA has been proposed by eliminating all the redundant logic operations present in conventional CSLA. In the proposed scheme calculation of final-sum is scheduled after carry select (CS) operation we have eliminated all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for CSLA. Bit patterns of two anticipating carry words (corresponding to cin =0and1) and fixed in bits are used for logic optimization of CS and generation units, by using optimized logic units an efficient CSLA design is obtained The proposed CSLA design involves significantly less area and low power than the recently proposed BEC-based CSLA. The proposed CSLA design is best for square-root (SQRT) CSLA because of the less area and low power. Keywords: conventional carry select adder, binary to excess-1 converter (BEC), proposed CSLA.

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Published

2016-10-30

How to Cite

Krishnamurthy2, D. K. P. (2016). DESIGN OF AREA EFFICIENT AND POWER OPTIMIZED CARRY SELECT ADDER. International Journal of Engineering Science and Generic Research, 2(5). Retrieved from https://ijesar.in/index.php/ijesar/article/view/35

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