DESIGN AND IMPLEMENTATION OF RECONFIGURABLE 64-POINT DISCRETE COSINE TRANSFORM (DCT) ARCHITECTURE

Abstract

The existing algorithms for approximation of DCT targets only on the DCT of small transform lengths, the main objective is reducing the power and calculation time. Multiplications are the operations in DCT which consumes majority of time and power and it is very complex to calculate the values of DCT. Approximation is needed in DCT for higher transform lengths as computational complication increases non-linearly with higher size lengths DCT. To offer lower circuit complexity and superior compression performance Multiplier-free approximate DCTs have been implemented which can be easily implemented in VLSI hardware by using only addition operation and subtraction operations. Thus, compared to integer and conventional DCTs, approximated DCTs result in reduction of the chip area as well as in power consumption. In this paper, here an algorithm is presented for approximation of DCT where an approximate DCT of length N could be derived from pair of DCTs of length (N/2) at cost of N additions. This algorithm is highly scalable for hardware as well as software implementation of DCT of higher lengths and it make use of the existing approximation of 8-point DCT to obtain approximate DCT of any power of 2 length{N>8}.It involves lower arithmetic complexity compared with the other existing approximation algorithms. It provides better image and video compression performance then the existing approximation methods. A fully scalable reconfigurable parallel architecture for computation of approximate 32-point DCT based on algorithm is implemented, The interesting feature of this architecture is that it could be configured for the computation of a 32-point DCT (or) for parallel computation of two 16-point DCTs (or) for parallel computation of four 8-point DCTs with less control overhead. A fully scalable reconfigurable parallel architecture for computation of approximate 32-point DCT extended to 64-point DCT based on same algorithm, it also could be configured for the computation of a 64-point DCT (or) for parallel computation of two 32-point DCTs (or) for parallel computation of four 16-point DCTs (or) for parallel computation of eight 8-point DCTs with less control overhead. A reconfigurable 32-point discrete cosine transform (DCT) and 64-point discrete cosine transform (DCT) architecture is simulated and synthesized by Xilinx 14.2 tool. KEYWORDS: DCT. Approximation of DCT, Scalable DCT, Reconfigurable DCT.