Design of 64-Bit Vedic Multiplier and Square Architectures
The design of high speed multiplier and squaring architectures based upon ancient Indian Vedic mathematics sutras. In this work, all the partial products are adjusted using concatenation operation and are added using single carry save adder instead of two adders at different stages. The high speed Vedic multiplier architecture is then used in the squaring modules. The reduced number of computations in multiplication due to adjusting using concatenation operation and one carry save adder only. The 64 bit Vedic multiplier and squaring architectures are designed by using Xilinx Spartan-3E FPGA. Keywords: Urdhava-Tiryakbhyam, Dwandwa-yoga, Multiplier, Square, IXI.
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International Journal of Engineering Science and Generic Research (IJESAR) by Articles is licensed under a Creative Commons Attribution 4.0 International License.