Design of radix 2 and radix4 multipliers with BIST

Abstract

In VLSI Industry testing is an essential process for making the assurance functionality of the chip. This paper is focusing on one of the test methodology called built-in-self-test (BIST).To introduce a novel test pattern generator (TPG) called Johnson counter for test the modules of the chip.TPG is generated here with the re-configurable Johnson counter and a LFSR generated seed values. Bit EX-OR operation is performed between the re-configurable Johnson counter and the seed. The proposed gray counter TPG was produced using Gray counter and Decoder. The Area and power optimization is achieved. Bist using radix2 multiplier with Gary tpg. We are extended Bist using radix4 multiplier with Gary tpg is coded using VERILOG HDL and simulations, synthesis were performed with Xilinx 13.2 tool. Keywords: Built-in-self-test (BIST), Test Pattern Generator (TPG), Linear feedback shift registers (LFSR).