Design of SPI Bus Protocol with Built-In-Self-Test using CA

Abstract

The Serial-Peripheral Interface (SPI) protocol is one of the important bus protocols for connecting with peripheral devices form microprocessor. The complexity of the circuits has aroused with the enormous advancement of IC technology. So, in order to lessen the product failure self-testability in hardware is demanded a lot in recent times. The necessity of self-testability will lead to a solution called Built-in-self-test (BIST). BIST is an effective solution to reduce the huge circuit testing cost. This paper represents design of SPI protocol with BIST using CA. Cellular automata pattern generator used instead of LFSR for high randomness To accomplish compact, stable and reliable data transmission, the SPI is designed with Verilog HDL Keywords: Serial-Peripheral Interface; Embedded built-in self-test architecture; Verilog HDL;