Vol. 4 No. 4 (2018)

Articles

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  Design of High Performance S-Box for AES 256 Bit using Galois Field (28)

  Sulla Ravali, Arunkumar Madupu

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• Design of Area Efficient and High performance of Scalable and Reconfigurable Approximation of DCT

  B. Yamini, Dr. M. Santhosh

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• An Efficient Algorithm for High Throughput and Low Power for Security Application’s

  Bathini Surekha, Arunkumar Madupu

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• Design and Implementation of 64 Bit Vedic Multiplier Based On Different Adder Structures on Verilog HDL

  Rakesh Raju Nadimetla, Lakshmi Bhavani

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• Implementation of Jacobi Iterative Solver using Verilog HDL

  Asmita Prabhakar Wakchaure, Ms. Anitha Patibandla

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• Application of ECC to Parallel Filter in Signal Processing Circuits

  Bikki Sravya, Ms.Anitha Patibandla

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• High Speed Computing Pipe lined Architecture of Elliptic Curve Scalar Multiplication over GF (2m)

  Dipali Arvind Bhalla, Ms. M. Anusha

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• Design and Implementation of an Efficient Bist for Digital Multipliers and Radix-4 Pipelined Multiplier on FPGA

  Gella Akhila, Syeda Yasmeen Sultana

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• A High Performance (72, 64) SEC-DAEC codes for ECC’S

  Joshi Prerana, Ms.M. Anusha

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• AN EFFICIENT BLOWFISH ALGORITHM BY USING 512 ROM

  Kamera Nagarani, Harishanker Srivatsav

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• Design and Implementation of Optimized New Full Adder\Full Subtractor Using Reversible Logic Gates

  Mahathi Anasurya Bhaskaruni, Sk.Dariya Saheb

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• 16 bit Design of adder subtractor circuit with optimized quantum cost using Feynman, PFAG and WG Gate

  Prabhat Kumar, Kamal Niwaria

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• THE THE PROBLEM OF PURCHASE TAXATION OF A COMPANY CAR IN THE VISEGRAD GROUP COUNTRIES ON THE EXAMPLE OF POLAND AND THE CZECH REPUBLIC

  Magdalena Sylwia Jarczok-Guzy

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• A REVIEW ON KRIMI ROGA IN CHILDREN W.S.R. TO WORM INFESTATIONS

  Dr Jyoti Kaushik, Dr Koushik Baishya, Dr Shilpi Sharma, Dr Rakesh Sharma

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• Optimizing the implementation of Radix-2 and Radix-4 Fast Fourier Transform Butterflies with Decimation in Time

  Vishnupriya Cheerla, Lavanya Nalluri

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