Optimizing the implementation of Radix-2 and Radix-4 Fast Fourier Transform Butterflies with Decimation in Time

Abstract

In FFT computation, the butterflies play a central role, since they allow the calculation of complex terms. Therefore, the optimization of the butterfly can contribute for the area reduction in FFT architectures. In this paper we exploit different addition schemes in order to improve the efficiency of 16-Point width radix-2 and radix-4 FFT butterflies. Combinations of simultaneous addition of three and seven operands are inserted in the structures of the butterflies in order to produce area efficient structures. The used additions schemes include Carry Save Adder (CSA), and adder compressors. The radix-2 and radix-4 butterflies were implemented in hardware description language and synthesized in Xilinx ISE 14.7. The main results show that both radix-2 and radix-4 butterflies, with CSA, are more efficient when compared with the same structures with other adder circuits.

Keywords: FFT; Radix-2 butterfly; Radix-4 butterfly.