A High Performance (72, 64) SEC-DAEC codes for ECC’S

Authors

  • Joshi Prerana PG Scholar at Malla Reddy College of Engineering and Technology, Hyderabad
  • Ms.M. Anusha Associate Professor at Malla Reddy College of Engineering and Technology, Hyderabad.

Abstract

Single error correction and double-adjacent error correction (SEC–DAEC) codes are a type of error correction codes (ECCs) capable of correcting single and double-adjacent errors. They are useful in applications where multiple adjacent errors may occur, such as space or avionics. ECC encoders and decoders have a regular structure that makes it easier to accommodate them into field-programmable gate arrays (FPGAs). This brief proposes methods to optimize the decoder of SEC–DAEC codes when implemented in an FPGA, reducing the resource utilization when compared with the conventional implementations.

Index Terms: Error correction codes (ECCs), field-programmable gate arrays (FPGAs), look up tables (LUTs), single; Error correction and double-adjacent error correction (SEC–DAEC).

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Published

2018-07-26

How to Cite

Prerana, J., & Anusha, M. (2018). A High Performance (72, 64) SEC-DAEC codes for ECC’S. International Journal of Engineering Science and Generic Research, 4(4). Retrieved from https://ijesar.in/index.php/ijesar/article/view/136

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Articles