Design and Implementation of 64 Bit Vedic Multiplier Based On Different Adder Structures on Verilog HDL

Authors

  • Rakesh Raju Nadimetla Student at Bandari Srinivas Institute of Technology, J.N.T.U.H affiliated college.
  • Lakshmi Bhavani Associate Professor and Head of the Department at Bandari Srinivas Institute of Technology, Hyderabad.

Abstract

Now a day it is indeed to design and implement an adiabatic logic in Vedic multiplier. Normally the power consumption was the main thing to remember before designing and implementing. So, the main aim to concentrate on the power consumption is very important. Various Adder topologies like Ripple Carry Adder (RCA), Carry Select Adder (CSA), Square Root Carry Select Adder (SQRT-CSA), Common Boolean Logic (CBL) and Binary to Excess one Converter (BEC) are used to compare area, delay and power. Designing is done for 8-bit, 16-bit, 32-bit and 64-bit Vedic multiplier using the above adders. And in Proposed design the Vedic multiplier is designed using Hybrid adder, due to the we can get reduced area occupation, less delay with low power consumption.

Keywords: Vedic Multiplier, RCA, CBL, BEC, CSA, SQRT-CSA, Design Compiler, Power, Delay, Area.

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Published

2018-07-26

How to Cite

Nadimetla, R. R., & Bhavani, L. (2018). Design and Implementation of 64 Bit Vedic Multiplier Based On Different Adder Structures on Verilog HDL. International Journal of Engineering Science and Generic Research, 4(4). Retrieved from https://ijesar.in/index.php/ijesar/article/view/131

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