Design of Area Efficient and High performance of Scalable and Reconfigurable Approximation of DCT

Authors

  • B. Yamini PG Scholar, M.Tech, Dept of ECE Anurag Group of Institutions, Hyderabad, India.
  • Dr. M. Santhosh Associate Professor, M.Tech, Anurag Group of Institutions, Hyderabad, India.

Abstract

The Digital image processing (DIP) has started as pioneer as a constituent of the digital signal processing (DSP) and emerged as the leader in very short time. Its prominence has kept on increasing in all research fields varying from low-level applications to high-level applications. The image and the video compression is a key operation in it and in past years various compression algorithms are proposed in the literature, but achieving the desired performance is still a challenging task.  The introduction of the Discrete Cosine Transform (DCT) has successfully overcome the existing algorithm issues in an effective manner and has replaced the traditional Fast Fourier Transform (FFT). The DCT has the ability to consider the real component of the image data while the earlier FFT his miserably failed in this aspect. The proposed design is used for the computation of a 32-point DCT or for parallel computation of four 16-point DCTs or eight 8-point DCTs. The proposed method achieves the lower arithmetic complexity as well as computational complexity over traditional methods.The DCT used in the image compression can be replaced with the modified approximation DCT.

Keywords: Discrete Cosine Transform,  Image and the video compression,  8-point DCTs

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Published

2018-07-12

How to Cite

Yamini, B., & Santhosh, D. M. (2018). Design of Area Efficient and High performance of Scalable and Reconfigurable Approximation of DCT. International Journal of Engineering Science and Generic Research, 4(4). Retrieved from https://ijesar.in/index.php/ijesar/article/view/129

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