16 bit Design of adder subtractor circuit with optimized quantum cost using Feynman, PFAG and WG Gate


  • Prabhat Kumar PG Scholar, Dept of ECE, RKDF 1st Bhopal (Sarvepalli Radhakrishnan University, Bhopal)
  • Kamal Niwaria Assistant Professors ECE Department RKDF Institute of Science & Technology Sarvepalli Radhakrishnan University, Bhopal.


Low power effective advanced gadgets are focus of specialists as of late. This point pulled in specialists to center around the reversible advanced circuit configuration approach. In perfect circumstances reversible circuits produce zero power misfortune with enhanced execution. Reversible circuit configuration approach is progressively connected in the territory of DNA figuring, low power CMOS outline, nanotechnology, quantum processing and optical registering and so on. This paper presents two plan approaches for reversible acknowledgment of 16-bit viper subtractor circuit with streamlined quantum cost.

These plans are contrasted and existing outlines on some chose execution parameters, for example, add up to number of reversible doors, trash yields and quantum cost. The proposed outline for 16-bit viper subtractor circuit utilizing reversible approach reenacted utilizing Modelsim apparatus and incorporated for Xilinx Spartan 3E with Device XC3S500E with 200 MHz recurrence. This enhanced circuit might be used further for the outlining of low power registering gadgets.

Keywords: Reversible Logic Gates; Quantum Cost; Garbage Outputs; 16-Bit Adder-Subtractor Circuit; PFAG gate; WG gate.




How to Cite

Kumar, P., & Niwaria, K. (2018). 16 bit Design of adder subtractor circuit with optimized quantum cost using Feynman, PFAG and WG Gate. International Journal of Engineering Science and Generic Research, 4(4). Retrieved from https://ijesar.in/index.php/ijesar/article/view/144