Design of 16 Bit Adder Subtractor with PFAG and TG Gates Using Verilog HDL

Authors

  • Prabhat Kumar Pg Scholar, Dept. of ECE, RKDF Ist Bhopal (Sarvepalli Radhakrishnan University, Bhopal
  • Dr.Bharti Chourasia HOD Associate Professor, EC. Dept. RKDF Institute of Science & Technology Sarvepalli Radhakrishnan University, Bhopal.
  • Kamal Niwaria Niwaria Assistant Professor, EC. Dept. RKDF Institute of Science & Technology Sarvepalli Radhakrishnan University, Bhopal.

Abstract

Reversible logic has extensive applications in quantum computing, low power VLSI design, quantum dot cellular automata and optical computing. While several researchers have investigated the design of reversible logic elements, there is not much work reported on reversible binary subtractors. In this paper, we propose the design of a new reversible gate called TR gate. Further, we investigate the design of reversible binary subtractors based on the proposed TR gate. The proposed TR gate is better for designing reversible binary subtractor compared to such gates discussed in literature in terms of quantum cost, garbage outputs and complexity of gates.

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Published

2018-09-15

How to Cite

Kumar, P., Chourasia, D., & Niwaria, K. N. (2018). Design of 16 Bit Adder Subtractor with PFAG and TG Gates Using Verilog HDL. International Journal of Engineering Science and Generic Research, 4(5). Retrieved from https://ijesar.in/index.php/ijesar/article/view/148

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