Design and Implementation of Optimized New Full Adder\Full Subtractor Using Reversible Logic Gates
Reversible logic is most popular concept in energy efficient computations and this will be demand for upcoming future computing technologies. Reversible logic is emerging as an important research area and it will be having wide applications in many fields such as optical information processing, quantum computing and Low power CMOS design. Under ideal conditions, the reversible logic gates will produce zero power dissipation. So this concept will helpful for Low power VLSI design. This paper will proposes the design of Full adder/subtractor circuit using fault tolerant reversible gates. The design can work singly as an adder/subtractor. The proposed design offers less hardware complexity and is efficient in terms of gate count, delay, constant inputs and garbage outputs compared to previous Fault tolerant Full Adder/Subtractor design. A parallel adder/subtractor design using fault tolerant reversible gates also proposed in this paper. The proposed circuits will be simulated using Xilinx ISE 14.7v simulator and implemented in Xilinx FPGA platform.
Keywords: Adder/Subtractor, Parity preserving reversible gates, Parallel Adder/Subtractor, Reversible logic gates.
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