Vol. 2 No. 4 (2016)

Articles

• FPGA based Performance Analysis of Micro programmed FIR Filters using Multipliers

  Pathapati Tanuja1, B.Bhavani 2

  • FULLTEXT PDF

• A LOW POWER 32-BIT MAC UNIT DESIGN USING VEDIC MUTIPLIER AND BRENT-KUNG ADDER

  Bhavana Paramkusham1, T. Kavitha2

  • FULLTEXT PDF

• A Radiation-Hardened AMBA Bus

  Gourav Deep Kaur Bal

  • FULLTEXT PDF

• Design of 32 bit high speed Six stage Pipeline RISC processor for Convolution

  Rudraram Sirisha1, Er. Nuli Namassivaya2

  • FULLTEXT PDF

• Design and Implementation of Area Efficient S-Box for Fully Pipelined AES

  1Mrs.Kondisetti Jyothi, 2Mr.Pattem Sampath Kumar, 3Mrs.Velaga Rajya Lakshmi,

  • FULLTEXT PDF

• Design of Four Port Router for Network on Chip Using VERILOG

  Ujjwal Kaushik1, Shubhangi Jaiswal2

  • FULLTEXT PDF

• Design and implementation of UART with BIST Capability

  BAPATLA PRATYUSHA1, M. SRINIVASARAO2,

  • FULLTEXT PDF

• A novel bus Design Technique for On Chip buses to resolve Bus Deadlock

  1 Mohammed Anjum, 2 MD.Mukram Ali,

  • FULLTEXT PDF