Design of 32 bit high speed Six stage Pipeline RISC processor for Convolution

Authors

  • Rudraram Sirisha1, Er. Nuli Namassivaya2 1 PG Research Scholar, Department of ECE, MVSR Engineering College, Hyderabad, India sirisha.siri147@gmail.com 2 Associate Professor, Department of ECE, MVSR Engineering College, Hyderabad, India

Abstract

Many algorithms have been design in order to accomplish an improved the performance of the filters by using the convolution design. The architecture of the proposed RISC CPU is a uniform 32-bit instruction format, single cycle non pipelined processor. It has load/store architecture, where the operations will only be performed on registers, and not on memory locations. A total of 27 instructions are designed in initial development step of the processor. The instruction set consists of Register, Logical, Immediate, Jump, Load, store type of instruction. The combined advantages RISC processor such as high speed efficient and operation specific design possibilities have been analyzed. In this paper we have implemented 32 bit 6 stage RISC processor to perform circular convolution at different modules of RISC processor like execute unit along with ALU, Instruction fetch along with instruction memory, decode unit, resistor unit, data memory has been implemented .For performance improvement apply the pipeline stages to the RISC architecture, in this paper we proposed the 5 stage and 6 stage pipeline RISC processor .In this compare the both pipeline stages. Keywords: RISC.

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Published

2016-08-30

How to Cite

Namassivaya2, R. S. E. N. (2016). Design of 32 bit high speed Six stage Pipeline RISC processor for Convolution. International Journal of Engineering Science and Generic Research, 2(4). Retrieved from https://ijesar.in/index.php/ijesar/article/view/29

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