Design of Four Port Router for Network on Chip Using VERILOG

Abstract

Multiprocessor system on chip (SOC) has emerged as a new trend for system on chip design but the wire and power design constraints are forcing to adopt new designs methodologies. Researchers has pursued a solutions to this problem i.e. Network on Chip (NOC). Network on chip is a communication system on an integrated circuits, typically between intellectual property (IP) cores in a system on a chip.[1] Network on chip architecture better supports the integration of SOC consists of on chip packet switched networks. We has developed a Router a packet based protocol. In this Router we have taken functionality references from an actual Router the design is being implemented on single chip using Verilog code. Keywords: FIFO, FSM, Network-On-Chip, Register Blocks, and Router Simulation.