Design of Four Port Router for Network on Chip Using VERILOG

Authors

  • Ujjwal Kaushik1, Shubhangi Jaiswal2 1ASIC Verification Engineer (Tevatron Technologies Pvt. Ltd.) 2Department of Electrical, Electronics and Communication Engineering, M.Tech in VLSI, Jayoti Vidyapeeth Women’s University, Jaipur, Rajasthan, India

Abstract

Multiprocessor system on chip (SOC) has emerged as a new trend for system on chip design but the wire and power design constraints are forcing to adopt new designs methodologies. Researchers has pursued a solutions to this problem i.e. Network on Chip (NOC). Network on chip is a communication system on an integrated circuits, typically between intellectual property (IP) cores in a system on a chip.[1] Network on chip architecture better supports the integration of SOC consists of on chip packet switched networks. We has developed a Router a packet based protocol. In this Router we have taken functionality references from an actual Router the design is being implemented on single chip using Verilog code. Keywords: FIFO, FSM, Network-On-Chip, Register Blocks, and Router Simulation.

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Published

2016-08-30

How to Cite

Jaiswal2, U. K. S. (2016). Design of Four Port Router for Network on Chip Using VERILOG. International Journal of Engineering Science and Generic Research, 2(4). Retrieved from https://ijesar.in/index.php/ijesar/article/view/27

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Articles