Design and implementation of UART with BIST Capability

Authors

  • BAPATLA PRATYUSHA1, M. SRINIVASARAO2, 1Department of ECE, QIS COLLEGE OF ENGINEERING&TECHNOLOGY, Ongole, India (PG Scholar) E-mail: bpratyusha24@gmail.com 2Department of ECE, QIS COLLEGE OF ENGINEERING&TECHNOLOGY, Ongole, India (Associate Professor)

Abstract

In today’s life the most manufacturing process are extremely complex, including manufactures to consider testability as a requirement to assure the reliability and functionality of each of their designed circuits. One of the most popular test techniques is called built-in –self-test (BIST). BIST is a design technique that allows a system to test automatically itself with slightly larger system size. a universal asynchronous receiver and transmitter(UART) with enabled BIST capability has the objective of testing the UART on chip itself and no external devices are required to perform the test. This paper focuses on the TRA (test response analyzer), circuit of BIST, in this paper, in previous design TRA compares the results with ROM values, proposed design implemented with simple MISR circuit. The simulation result performance achieved by BIST enabled UART architecture through VHDL programming is enough to compensate the extra hardware needed in the BIST architecture. This technique generate random test pattern automatically, so it can provide less test time compared to an externally applied test pattern and helps to achieve much more productivity at the end. Keywords: VLSI, BIST, UART, VHDL, Cellular automata.

Downloads

Published

2016-08-30

How to Cite

SRINIVASARAO2, B. P. M. (2016). Design and implementation of UART with BIST Capability. International Journal of Engineering Science and Generic Research, 2(4). Retrieved from https://ijesar.in/index.php/ijesar/article/view/26

Issue

Section

Articles