Vol. 4 No. 6 (2018)

Articles

• DESIGN OF FAULT TOLERANT PARALLEL FFT'S USING PARSEVAL CHECK

  K. Vasundhara, V. Lakshmi Prasanna

  • FULLTEXT PDF

• DESIGN AND IMPLEMENTATION OF AN EFFICIENT BIST FOR RADIX-4 BOOTH MULTIPLIER ON FPGA

  Mohd Abdul Raheem, Dr. Mohammad Iliyas, Dr. Farha Anjum

  • FULLTEXT PDF

• A NOVEL VLSI ARCHITECTURE FOR RADIX-2 AND RADIX-4 BUTTERFLIES IN FFT USING DECIMATION IN TIME

  Mrs. Sabiha Perveen, Dr. Mohammad Iliyas, Dr. Farha Anjum

  • FULLTEXT PDF

• IMPLEMENTATION OF ON-CHIP ADVANCE MICROCONTROLLER BUS ARCHITECTURE SHARED BUS MULTI-PROCESSOR SOC USING DIFFERENT ARBITRATION ALGORITHM

  N Malathi, E Swetha

  • FULLTEXT PDF