AN ULTRA-HIGH THROUGHPUT AND FULLY PIPELINED IMPLEMENTATION OF MODIFIED-AES ALGORITHM ON FPGA

Authors

  • V Narendra Babu Dept of ECE, Sri Venkateswara College of Engineering and Technology, Tirupati.
  • Jakkidi Vamshi Kanth Reddy Research Scholar, Vedic School of VLSI Design, Hyderabad.

Abstract

This paper proposes Rijndael encryption and decryption which runs its symmetric cipher algorithm called AES. The four stages of AES are divided to ten pipeline stages with the modification that the Byte Substitute is operated after the Shift Row block. This proposed swapping operation has no effect on the Modified AES encryption algorithm. This swapping modernizes the process in parallel manner. This technique is implemented using composite field arithmetic byte substitution for S box. The high throughput can be achieved by inserting some registers in appropriate points making the delay shortest. The simulation results show that the proposed AES has higher throughput with a saving hardware area.

Keywords: Sub Bytes, Shift Rows. Key expansion, pipeline, GF (24)2.

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Published

2019-03-11

How to Cite

Babu, V. N., & Reddy, J. V. K. (2019). AN ULTRA-HIGH THROUGHPUT AND FULLY PIPELINED IMPLEMENTATION OF MODIFIED-AES ALGORITHM ON FPGA. International Journal of Engineering Science and Generic Research, 5(2). Retrieved from https://ijesar.in/index.php/ijesar/article/view/161

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Articles