A Novel VLSI Architecture for Convolution using 32 bit Higher Radix Algorithm

Authors

  • 1 Akula Saritha, 2 K. Tarangini 1Student at Vidya Jyothi Institute of Technology, Aziz Nagar, Hyderabad, India. 2Assistant Professor at Vidya Jyothi Institute of Technology, Aziz Nagar, Hyderabad, India.

Abstract

Convolution and deconvolution algorithms play a key role in digital processing applications. They involve many multiplication and division steps and consume a lot of processing time. As such, they play a vital role in determining the performance of the digital signal processor. Convolution and deconvolution implemented with Vedic mathematics proved fast as compared to those using conventional methods of multiplication and division. This paper presents a novel VHDL implementation of convolution and deconvolution algorithm with multiplier using radix-256 booth encoding to reduce the partial product rows by eight fold and carry propagate free redundant binary addition for adding the partial products, thus, contributing to higher speed. The design had been implemented for 16 bit signed and unsigned sequences. The delay was reduced by 18.27%. The entire design was implemented in Xilinx ISE 13.1 targeted towards Virex-7. Keywords - Convolution and deconvolution, Radix-256, Redundant binary (RB) addition, Xilinx ISE.

Downloads

Published

2017-10-30

How to Cite

Tarangini, 1 A. S. 2 K. (2017). A Novel VLSI Architecture for Convolution using 32 bit Higher Radix Algorithm. International Journal of Engineering Science and Generic Research, 3(5). Retrieved from https://ijesar.in/index.php/ijesar/article/view/84

Issue

Section

Articles