Design and Implementation of Pipelined SEC-DEAC (72,64) Codes

Authors

  • 1 Yogesh Eppa , 2 Ganji Annapurna 1 PG Scholar, Vidya Jyothi Institute of Technology, Aziz Nagar, Hyderabad, India. 2Assistant Professor, Vidya Jyothi Institute of Technology, Aziz Nagar, Hyderabad, India.

Abstract

Single error correction and double-adjacent error correction (SEC–DAEC) codes are a type of error correction codes (ECCs) capable of correcting single and double-adjacent errors. They are useful in applications where multiple adjacent errors may occur, such as space or avionics. ECC encoders and decoders have a regular structure that makes it easier to accommodate them into field-programmable gate arrays (FPGAs). This brief proposes methods to optimize the decoder of SEC–DAEC codes when implemented in an FPGA, reducing the resource utilization when compared with the conventional implementations. The implementation of two codes, a (72, 64) SEC–DAEC and a (72, 64) SEC–DAEC with pipeline, show that the proposed designs reduce the resource utilization of the correction circuit when comparing it with the conventional designs.

 Index Terms: Error correction codes (ECCs), field-programmable gate arrays (FPGAs), lookup tables (LUTs), single error correction and double-adjacent error correction (SEC–DAEC).

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Published

2017-10-30

How to Cite

Annapurna, 1 Y. E. , 2 G. (2017). Design and Implementation of Pipelined SEC-DEAC (72,64) Codes. International Journal of Engineering Science and Generic Research, 3(5). Retrieved from https://ijesar.in/index.php/ijesar/article/view/82

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