Design of High-Performance Montgomery Modular Multiplication

Authors

  • 1DIBBAGANDLA SURENDRA 2G.JAGADEESWAR REDDY 1 PG Scholar, Vaagdevi Institute of Technology and Science, Proddatur, Kadapa (dist), AP. India. 2Director cumPrincipal, Vaagdevi Institute of Technology and Science, Proddatur, Kadapa (dist), AP. India.

Abstract

The proposed multiplier receives and outputs the data with binary representation and uses only one-level carry-save adder (CSA) to avoid the carry propagation at each addition operation. This CSA is also used to perform operand precomputation and format conversion from the carry save format to the binary representation, leading to a low hardware cost and short critical path delay at the expense of extra clock cycles for completing one modular multiplication. To overcome the weakness, a configurable CSA (CCSA), which could be one full-adder or two serial half-adders, is proposed to reduce the extra clock cycles for operand precomputation and format conversion by half. In addition, a mechanism that can detect and skip the unnecessary carry-save addition operations in the one-level CCSA architecture while maintaining the short critical path delay is developed.

Index Terms: Carry-save addition, low-cost architecture, Montgomery modular multiplier, public-key cryptosystem.

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Published

2017-10-30

How to Cite

REDDY, 1DIBBAGANDLA S. 2G.JAGADEESWAR. (2017). Design of High-Performance Montgomery Modular Multiplication. International Journal of Engineering Science and Generic Research, 3(5). Retrieved from https://ijesar.in/index.php/ijesar/article/view/74

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