DESIGN OF FIR FILTER USING VEDIC MULTIPLIER WITH COMPRESSORS AND PROPOSED CSLA

Abstract

An adder and a multiplier are main components of an arithmetic unit. An efficient adder and multiplier design, essentially improves the performance of a complex DSP system. Carry Select Adder (CSA) is a fastest adder used in many processors to accomplish fast arithmetic function. Many different adder architecture designs have been developed to increase the efficiency of the adder. It is very commonly known that per second any processor can perform millions of work functions in semiconductor industry. In this paper, we propose a technique for designing of FIR filter using multiplier based on compressor and a proposed carry select adder. Unnecessary logic operations are removed to design an efficient carry select Adder. The proposed FIR filter is simulated and synthesized by using Xilinx ISE.

Keywords: Carry Select Adder (CSA), Vedic multiplier using Compressor, FIR Filter.