A HIGH PERFORMANCE (72, 64) SINGLE ERROR CORRECTION-DOUBLE ADJACENT ERROR

Authors

  • Kavitha Bollineni M.tech Scholar, Dept of ECE, QIS Institute of Technology, Ongole, India.
  • Mr. Saidulu Inamanamelluri Assistant Professor, Dept of ECE, QIS Institute of Technology, Ongole, India

Abstract

Single error correction and double-adjacent error correction (SEC–DAEC) codes are a type of error correction codes (ECCs) capable of correcting single and double-adjacent errors. They are useful in applications where multiple adjacent errors may occur, such as space or avionics. ECC encoders and decoders have a regular structure that makes it easier to accommodate them into field-programmable gate arrays (FPGAs). This brief proposes methods to optimize the decoder of SEC–DAEC codes when implemented in an FPGA, reducing the resource utilization when compared with the conventional implementations.

Index Terms: Error correction codes (ECCs), field-programmable gate arrays (FPGAs), look up tables (LUTs), single Error correction and double-adjacent error correction (SEC–DAEC).

Downloads

Published

2019-11-26

How to Cite

Bollineni, K., & Inamanamelluri, M. S. (2019). A HIGH PERFORMANCE (72, 64) SINGLE ERROR CORRECTION-DOUBLE ADJACENT ERROR. International Journal of Engineering Science and Generic Research, 5(6). Retrieved from https://ijesar.in/index.php/ijesar/article/view/173

Issue

Section

Articles