Babu, V. N. and Reddy, J. V. K. (2019) “AN ULTRA-HIGH THROUGHPUT AND FULLY PIPELINED IMPLEMENTATION OF MODIFIED-AES ALGORITHM ON FPGA”, International Journal of Engineering Science and Generic Research, 5(2). Available at: https://ijesar.in/index.php/ijesar/article/view/161 (Accessed: 16April2026).