2, C. K. C. A. Design and Implementation of 64-Bit Vedic Multiplier and Square Architectures. International Journal of Engineering Science and Generic Research, [S. l.], v. 3, n. 5, 2017. Disponível em: https://ijesar.in/index.php/ijesar/article/view/79. Acesso em: 19 apr. 2024.