KUMAR, P.; CHOURASIA, D.; NIWARIA, K. N. Design of 16 Bit Adder Subtractor with PFAG and TG Gates Using Verilog HDL. International Journal of Engineering Science and Generic Research, [S. l.], v. 4, n. 5, 2018. Disponível em: https://ijesar.in/index.php/ijesar/article/view/148. Acesso em: 27 jul. 2021.