TARANGINI, 1 A. S. 2 K. A Novel VLSI Architecture for Convolution using 32 bit Higher Radix Algorithm. International Journal of Engineering Science and Generic Research, [S. l.], v. 3, n. 5, 2017. Disponível em: https://ijesar.in/index.php/ijesar/article/view/84. Acesso em: 14 jul. 2026.