BABU, V. N.; REDDY, J. V. K. AN ULTRA-HIGH THROUGHPUT AND FULLY PIPELINED IMPLEMENTATION OF MODIFIED-AES ALGORITHM ON FPGA. International Journal of Engineering Science and Generic Research, [S. l.], v. 5, n. 2, 2019. Disponível em: https://ijesar.in/index.php/ijesar/article/view/161. Acesso em: 16 apr. 2026.