NADIMETLA, R. R.; BHAVANI, L. Design and Implementation of 64 Bit Vedic Multiplier Based On Different Adder Structures on Verilog HDL. International Journal of Engineering Science and Generic Research, [S. l.], v. 4, n. 4, 2018. Disponível em: https://ijesar.in/index.php/ijesar/article/view/131. Acesso em: 10 jun. 2026.