High Performance and Area Efficient VLSI Architecture for Advanced Encryption Standard Algorithm Using GF (28)

Abstract

An efficient implementation of the Advanced Encryption Standard (AES) Algorithm. The presented architecture is adapted for AES encryption, encryption/decryptiondesigns.TheSub, InvSubBytes operations are implemented using composite field arithmetic. Efficient architecture for performing the mix columns & inverse mix columns operation, which is the major operation in the Advanced Encryption Standard (AES) method of cryptography. In the implementation of this AES-256 algorithm has a plaintext of 128 bits and key of 256 bits size. The number of rounds of operations in AES- 256 is 14. The key generation process of AES 256 is different from other AES algorithms. Xilinx 13.2i software is used for simulation and optimization of the synthesizable VERILOG code. All the transformations of both Encryption, Encryption/Decryption designs

Keywords: RCA. NRCA, bit permutation, RBP.