Implementation of High Speed Single Error Correction–Double Adjacent Error Correction (72, 64) Codes

Abstract

Single error correction and double-adjacent error correction (SEC–DAEC) codes are a type of error correction codes (ECCs) capable of correcting single and double-adjacent errors. The existing methods (39, 32) Per-Bit Joined-Pattern Correction. In these technique having more delay, to overcome this problem (72, 64) SEC–DAEC with pipeline method. This brief proposes methods to optimize the decoder of SEC–DAEC codes when implemented in an FPGA, reducing the resource utilization when compared with the conventional implementations. The implementation of two codes, a (72, 64) SEC–DAEC and a (72, 64) SEC–DAEC with pipeline, show that the proposed designs reduce the resource utilization of the correction circuit when comparing it with the conventional designs.

Index Terms: Error correction codes (ECCs), field-programmable gate arrays (FPGAs), lookup tables (LUTs), single error correction and double-adjacent error correction (SEC–DAEC).