An Efficient Linear Convolution using Higher Radix Booth encoding, Algorithm

Authors

  • 1 Mudragada Siva Ramakrishna, 2Shilpa Samarla, 3 Seelam Srinivas Rao 1Student at Nalla Narsimha Reddy Educational Society Group of Institutions, Hyderabad, India. 2Assistant Professor at Nalla Narsimha Reddy Educational Society Group of Institutions, Hyderabad, India. 3Assistant Professor at Nalla Narsimha Reddy Educational Society Group of Institutions, Hyderabad, India.

Abstract

Convolution and deconvolution algorithms play a key role in digital processing applications. They involve many multiplication and division steps and consume a lot of processing time. As such, they play a vital role in determining the performance of the digital signal processor. Convolution and deconvolution implemented with Vedic mathematics proved fast as compared to those using conventional methods of multiplication and division. This paper presents a novel VHDL implementation of convolution and deconvolution algorithm with multiplier using radix-256 booth encoding to reduce the partial product rows by eight fold and carry propagate free redundant binary addition for adding the partial products, thus, contributing to higher speed. The design had been implemented for 16 bit signed and unsigned sequences. The delay was reduced by 18.27%. The entire design was implemented in Xilinx ISE 13.1 targeted towards Virex-7. Keywords - Convolution and deconvolution, Radix-256, Redundant binary (RB) addition, Xilinx ISE.

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Published

2017-12-31

How to Cite

3 Seelam Srinivas Rao, 1 M. S. R. 2Shilpa S. (2017). An Efficient Linear Convolution using Higher Radix Booth encoding, Algorithm. International Journal of Engineering Science and Generic Research, 3(6). Retrieved from https://ijesar.in/index.php/ijesar/article/view/90

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Articles