A Floating Point Multiplier Design Using Karatsuba and Urdhva-Tiryagbhyam Algorithms for High Speed Applications

Authors

  • A. Raviteja1, A. Jaya Lakshmi 2 1 PG Scholar, Vidya Jyothi Institute of Technology, Aziz Nagar, Hyderabad, India. 2Assistant Professor, Vidya Jyothi Institute of Technology, Aziz Nagar, Hyderabad, India.

Abstract

Floating Point Multiplication is mainly used for high   speed operations such as digital image processing and digital signal processing etc. But multiplication is a time taking and power consuming process. In this paper an IEEE754 floating point multiplier is designed and implemented which is efficient in terms of area and delay. For implementing unsigned binary multiplier for mantissa multiplication both Karatsuba and Urdhva- Tiryagbyam which is a sutra of Vedic mathematics is used. The multiplier is implemented using verilog, targeted on Spartan-3E

Keywords: Floating Point Multiplier, Urdhva-Tiryagbyam algorithm and karatsuba algorithm.

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Published

2017-10-30

How to Cite

2, A. R. A. J. L. (2017). A Floating Point Multiplier Design Using Karatsuba and Urdhva-Tiryagbhyam Algorithms for High Speed Applications. International Journal of Engineering Science and Generic Research, 3(5). Retrieved from https://ijesar.in/index.php/ijesar/article/view/77

Issue

Vol. 3 No. 5 (2017)

Section

Articles

License

Creative Commons LicenseInternational Journal of Engineering Science and Generic Research (IJESAR) by Articles is licensed under a Creative Commons Attribution 4.0 International License.