Design of Fully Pipelined 128-bit AES with S-Box by using Combinational Logic

Abstract

The Advanced Encryption Standard (AES) is considered to be the strongest encryption technique in cryptography. Advanced Encryption Standard (AES) is a symmetric key block cipher which will encrypt as well as decrypt the data block. The pre-computed values stored in a ROM based lookup table. In this implementation, all 256 values are stored in a ROM such implementation is expensive in terms of hardware. A more refined way of implementing the S-Box by using Composite field method through combinational logic. This S Box has the advantage of having small area occupancy. Hence it delivers high throughput optimizes the delay and reduces the area. The 128-bit Advanced Encryption Standard (AES) of fully Pipelined AES with Compact S-Box is simulated and synthesized by Xilinx 13.2 tool. Keywords: VLSI, AES, ENCRYPTION, DECRYPTION.