A review paper on AN EFFECTIVE FULL ADDER DESIGN using different logic style for low power dissipation

Authors

  • Yeshu Mishra, Khushboo Patni M.Tech (VLSI) Research Scholar, Dept of ECE, JVW, University, Rajasthan, India

Abstract

Adders are the key components in building of any digital circuits. They are used not only for addition but also used for multiplication & division too. Adders find a wide application in very large scale integrated circuits like in arithmetic logic circuits to application specific integrated circuits. At the same time, building low-power, high-performance full adder cells is of great interest. The objective of this paper is to give an overview of full adder implementation using various logic styles at 45 nm technology. Logic style is the supreme factor, which influence switching speed, delay & power dissipation. Different logic styles have been compared taking full adder design as a reference & power dissipation as a reference parameter. Simulation results of full adder at a technology of 45 nm have been provided. Keywords: Full adder, Complementary pass transistor, CMOS, Pass transistor, Transmission gate

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Published

2016-06-30

How to Cite

Patni, Y. M. K. (2016). A review paper on AN EFFECTIVE FULL ADDER DESIGN using different logic style for low power dissipation. International Journal of Engineering Science and Generic Research, 2(3). Retrieved from https://ijesar.in/index.php/ijesar/article/view/16

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Articles