IMPLEMENTATION OF OPTIMIZED VLSI ARCHITECTURE FOR CONVOLUTION AND DECONVOLUTION USING 32 BIT HIGHER RADIX ALGORITHM

Abstract

Convolution and deconvolution algorithms play a key role in digital processing applications. They involve many multiplication and division steps and consume a lot of processing time. As such, they play a vital role in determining the performance of the digital signal processor. Convolution and deconvolution implemented with Vedic mathematics proved fast as compared to those using conventional methods of multiplication and division. This paper presents a novel Verilog implementation of convolution and deconvolution algorithm with multiplier using radix-256 booth encoding to reduce the partial product rows by eight fold and carry propagate free redundant binary addition for adding the partial products, thus, contributing to higher speed. The design had been implemented for 32 bit signed and unsigned sequences. The delay was reduced by 18.27%. The entire design was implemented in Xilinx ISE 14.7 targeted towards Spartan 3E.

Keywords: Convolution and deconvolution, Radix-256, Redundant binary (RB) addition, Xilinx ISE.