A NOVEL VLSI ARCHITECTURE FOR RADIX-2 AND RADIX-4 BUTTERFLIES IN FFT USING DECIMATION IN TIME
In FFT computation, the butterflies play a central role, since they allow the calculation of complex terms. Therefore, the optimization of the butterfly can contribute for the power reduction in FFT architectures. Different addition schemes are exploited in order to improve the efficiency of 16 bitwidth radix-2 and radix-4 FFT butterflies. Combinations of simultaneous addition of three and seven operands are inserted in the structures of the butterflies in order to produce powerefficient structures. The used additions schemes include Carry Save Adder (CSA), and adder compressors.
The radix-2 and radix-4 FFT butterflies using CSA_FA/RCA_3-2 and 7-2_CSA_FA are implemented in 16 point DIT FFT.
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