Published: 2016-12-27

Title : Design of Fully Pipelined 128-bit AES with S-Box by using Combinational Logic

Author(s): SHAIK VAZID AHAMMED 1, JAI KUMAR VINAYAGAM 2
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Title : Designing Architecture for Communication between I2C (inter integrated circuit) and AHB (Advanced High Performance Bus

Author(s): Rubina Sultana 1, G.ARUNA2
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Title : Design and Implementation of High Speed Parallel Micro programmed FIR Filter using Wallace tree and Vedic Multiplier

Author(s): Neha Samreen1, S.Suneeta 2
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Title : CRYPTOGRAPHIC TECHNIQUE BY SQUARE MATRIX AND SINGLE POINT CROSSOVER ON BINARY FIELD

Author(s): MR.G.RAVI KISHORE 1, MS.SABA NAUSHEEN 2
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