Published: 2016-10-29

Title : Design and Implementation of MUX Based FIR filter with Hybrid Adder

Author(s): U.PRAVEEN KUMAR1, W.YASMEEN 2
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Title : DESIGN AND IMPLEMENTATION OF SEQUENTIAL AND PARALLEL MICROPROGRAMMED FIR FILTER

Author(s): S.Sravanthi1, K.Naga Koushil Reddy 2
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Title : Implementation of SHA-2(256) & SHA-3(512) Algorithms for Information Security

Author(s): M.Mounika1, T.Thammi Reddy 2
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Title : Quad-Fault Tolerant Architecture Design for Ripple Carry Adder

Author(s): Vayalasetti Swarnalatha1, Praveen Kumar Polisetty 2
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Title : Design of floating point multiplier using karatsuba - urdhava multiplier and koggestone adder

Author(s): U.Sudharani 1, K.Siva Sundari 2
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Title : DESIGN AND IMPLEMENTATION OF RECONFIGURABLE 64-POINT DISCRETE COSINE TRANSFORM (DCT) ARCHITECTURE

Author(s): Meesala Shiva Kumar 1, Dr. G V Maha Lakshmi 2
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Title : Design of SPI Bus Protocol with Built-In-Self-Test using CA

Author(s): GANTI PRAVEEN ANAND 1, N.LATHA 2
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Title : EFFICIENT SCALABLE FIR FILTER IMPLEMENTATION USING VEDIC MULTIPLIERS

Author(s): Chunduri Krishna Chaitanya1, K V S Sri Harsha2
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Title : FPGA Implementation of 16 bit MUX Based Multiplier

Author(s): Jaganmohan 1, K.RAMBABU 2
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Title : Design and Implementation of Area Efficient S-Box using Combinational logic with Pipelined AES

Author(s): G.Hymavathi 1, V.Venkanna 2
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Title : Design and Implementation of Convolution and Deconvolution by using Sutras

Author(s): Allakonda VamshiKrishna1, A Karthik2, Dr K Srinivasulu3
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Title : Design of radix 2 and radix4 multipliers with BIST

Author(s): A.SREENU NAIK 1, YELGAMONI RAVINDER 2
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Title : FPGA Realization of MUX Based FIR Filter Architecture

Author(s): K.Sabitha 1, S.Sreehari 2
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Title : DESIGN OF 64 bit MAC UNIT WITH VEDIC MULTIPLIER AND REVERSIBLE DKG GATE

Author(s): K.RAVI 1, MADARAPU AJITHRAO 2
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Title : Design and implementation of Floating point multiplication with Karatsuba-Urdhva multiplier and kogge stone adder

Author(s): DONURU MADHAVI 1, V.VENKANNA 2
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Title : Design and Implementation of Sequential and Parallel FIR Filters using Vedic Multiplier with Compressors

Author(s): APPAM TEJASWI 1, MADARAPU AJITHRAO 2
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Title : DESIGN OF EFFICIENT RECONFIGURABLE INTERPOLATION FILTER

Author(s): V. Rajendra chary 1, C. Pamuleti 2
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Title : Design of 64-Bit Vedic Multiplier and Square Architectures

Author(s): Kriti Rashmi Sinha 1, Pathloth Krishnamurthy 2
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Title : Design and Implementation of radix Booth Multiplier with BIST TPG

Author(s): K.Rajani 1, Prof.I.Venugopal 2
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Title : FPGA Implementation of Vedic ALU with Application Specific Reversible Gates

Author(s): Marri Vasudha 1, V.Suresh Kumar 2
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Title : Design of Reconfigurable Architecture for 64-point DCT

Author(s): M.PHANINDRA BABU 1, MADARAPU AJITHRAO 2
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Title : Design of Memory controller with AXI Bus interface

Author(s): 1 K.KRISHNAIAH, 2 YELGAMONI RAVINDER
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Title : DESIGN OF AREA EFFICIENT AND POWER OPTIMIZED CARRY SELECT ADDER

Author(s): Deepak Kumar1, Pathloth Krishnamurthy2
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Title : Design of Area Efficient Substitution-Box with Pipelined AES

Author(s): K.Keerthi Sucharitha 1, G. Hamarnath 2, T.Chakrapani3
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Title : RF Front-end Design of a Digital TV Receiver

Author(s): D. Sony Dr.G.V. Mahalakshmi
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