Published: 2018-07-09

Title : Design of High Performance S-Box for AES 256 Bit using Galois Field (28)

Author(s): Sulla Ravali, Arunkumar Madupu
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Title : Design of Area Efficient and High performance of Scalable and Reconfigurable Approximation of DCT

Author(s): B. Yamini, Dr. M. Santhosh
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Title : An Efficient Algorithm for High Throughput and Low Power for Security Application’s

Author(s): Bathini Surekha, Arunkumar Madupu
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Title : Design and Implementation of 64 Bit Vedic Multiplier Based On Different Adder Structures on Verilog HDL

Author(s): Rakesh Raju Nadimetla, Lakshmi Bhavani
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Title : Implementation of Jacobi Iterative Solver using Verilog HDL

Author(s): Asmita Prabhakar Wakchaure, Ms. Anitha Patibandla
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Title : Application of ECC to Parallel Filter in Signal Processing Circuits

Author(s): Bikki Sravya, Ms.Anitha Patibandla
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Title : High Speed Computing Pipe lined Architecture of Elliptic Curve Scalar Multiplication over GF (2m)

Author(s): Dipali Arvind Bhalla, Ms. M. Anusha
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Title : Design and Implementation of an Efficient Bist for Digital Multipliers and Radix-4 Pipelined Multiplier on FPGA

Author(s): Gella Akhila, Syeda Yasmeen Sultana
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Title : A High Performance (72, 64) SEC-DAEC codes for ECC’S

Author(s): Joshi Prerana, Ms.M. Anusha
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Title : AN EFFICIENT BLOWFISH ALGORITHM BY USING 512 ROM

Author(s): Kamera Nagarani, Harishanker Srivatsav
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Title : Design and Implementation of Optimized New Full Adder\Full Subtractor Using Reversible Logic Gates

Author(s): Mahathi Anasurya Bhaskaruni, Sk.Dariya Saheb
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