Published: 2017-10-20

Title : AN EFFICIENT AND HIGH PERFORMANCE SOVA DETECTOR ON FPGA

Author(s): 1 Gundaram Priyanka , 2 G.Ravi Kumar
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Title : A Novel VLSI Architecture for Convolution using 32 bit Higher Radix Algorithm

Author(s): 1 Akula Saritha, 2 K. Tarangini
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Title : Design and Implementation of Reconfigurable Architecture for 64-Point Discreet Cosine Transform

Author(s): 1 Sudidela Hanumanthareddy, 2 Shaik Rahamtula
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Title : Design and Implementation of Pipelined SEC-DEAC (72,64) Codes

Author(s): 1 Yogesh Eppa , 2 Ganji Annapurna
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Title : Design of High Performance and Efficient Blowfish Algorithm by using 512 ROM Based S-Box

Author(s): 1Mummadi Rajeswari, 2 Sandeep Chilumula
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Title : Symmetric transparent BIST for memory using March X algorithm

Author(s): 1G Dhanalakshmi, 2 SK SIRAJ
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Title : Design and Implementation of 64-Bit Vedic Multiplier and Square Architectures

Author(s): CH.Roja1, K. Chinna Akkaiah 2
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Title : Design and Implementation of a Pipelined 64 bit MAC Unit with Vedic Multiplier and Reversible DKG Gate

Author(s): 1 Akula Alivelu, 2 Sandeep Chilumula
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Title : A Floating Point Multiplier Design Using Karatsuba and Urdhva-Tiryagbhyam Algorithms for High Speed Applications

Author(s): A. Raviteja1, A. Jaya Lakshmi 2
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Title : Effective Implementation of Dual Key Based AES Encryption with Key Based S-Box Generation

Author(s): 1 Manohar Nagallapati, 2 K. Naveen Kumar Raju
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Title : Design of Optimized Radix-2 and Radix-4 Butterflies from FFT with Decimation in Time

Author(s): 1 K. MARYANGELEENA KONKARI, 2 V. RAMESH
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Title : Design of High-Performance Montgomery Modular Multiplication

Author(s): 1DIBBAGANDLA SURENDRA 2G.JAGADEESWAR REDDY
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Title : Design of modified Radix-10 parallel multiplier

Author(s): 1K.Prasanthi, 2 Mrs.P.Asiya Thapaswin
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Title : Design of Fault Tolerant Parallel FFTs using Parity SOS Scheme

Author(s): 1 GUDDETI SRAVANI, 2 D.GHOUSE KARIM
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