International Journal of Engineering Science and Generic Research

XOR FREE ADVENT OF CONVOLUTION ENCODER IMPLEMENTATION

Jaladurgam Venkata Anjan Kumar — 2019-03-11

This work presents a new algorithm to construct an XOR-Free architecture of a power efficient Convolution Encoder. Optimization of XOR operators is the main concern while implementing polynomials over GF (2), which consumes a significant amount of dynamic power. The proposed approach completely removes the XOR-processing operation of a chosen non-systematic, feed-forward generator polynomial and reduces the logical operators, thereby the decoding cost.

Index Terms: Convolution Codes, Common Sub expression Elimination, Finite State Machine, Forward Error Correction, FPGA, HDL, Modulo Adder.

AN ULTRA-HIGH THROUGHPUT AND FULLY PIPELINED IMPLEMENTATION OF MODIFIED-AES ALGORITHM ON FPGA

V Narendra Babu — 2019-03-11

This paper proposes Rijndael encryption and decryption which runs its symmetric cipher algorithm called AES. The four stages of AES are divided to ten pipeline stages with the modification that the Byte Substitute is operated after the Shift Row block. This proposed swapping operation has no effect on the Modified AES encryption algorithm. This swapping modernizes the process in parallel manner. This technique is implemented using composite field arithmetic byte substitution for S box. The high throughput can be achieved by inserting some registers in appropriate points making the delay shortest. The simulation results show that the proposed AES has higher throughput with a saving hardware area.

Keywords: Sub Bytes, Shift Rows. Key expansion, pipeline, GF (2⁴⁾².

DESIGN AND IMPLEMENTATION OF AN OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER

Kurukuti Naresh — 2019-03-11

The ever increasing applications of integrated circuits in the day-to-day useful electronic gadgets are the driving force for the development of low power designs of configurable hardware designs. High speed and low power are the main parameters that are targeted by modern circuit designers.. Multipliers are the very important logic operational unit of any processing unit in digital signal processing applications. The speed and performance of multiplier is among the efficiency improvement parameters of any digital hardware design. Another important feature of hardware designs is self-testing ability. This feature provides reliability to the hardware mainly in case of configurable hardware applications.

BIST based approach is used for the implementation of a multiplier using a configurable hardware. A 4-bit low power multiplier design is used as a test logic design. The multiplier design is implemented using gate level architecture representation for realizing the low-power hardware. A gate level combination is used to generate a half-adder and a full-adder design. These adder design block are used in combination to generate the multiplier using the adder terms.

For the BIST implementation, a test pattern generator with random output value is required. For TPG realization, a low-power modified design of linear-feedback-shift-register (LFSR) is used in this design implementation. A 3-register is used for the generation of a 4-bit random number. It is a comparative low power design realization as compared to other existing test power generator designs. Most of the existing TPG have a register-to-bit ratio of ‘1’. In this project, the TPG has a register-to-bit ration of 3:4. This circuit generates a 4-bit random value using only 3-registers, so relative low power consumption is caused by this circuit. In this project, using this BIST technique various multipliers are implemented and compared.

Keywords: Built-In-Self-Test, Test Pattern Generator, Linear Feedback Shift Register, Xilinx.

DESIGN OF CARRY SELECT ADDER FOR LOW POWER AND HIGH SPEED VLSI APPLICATIONS USING HYBRID ADDER

Gudiselapalli Jagan — 2019-03-11

In this paper, Carry Select Adder (CSA) structures are proposed utilizing parallel prefix adders. Rather than utilizing double Ripple Carry Adders (RCA), parallel prefix Adder i.e., Koggestone (KSA) Adder is utilized to outline Regular Linear CSA. Adders are the essential building hinders in computerized coordinated circuit based outlines. Swell Carry Adder (RCA) gives the most minimized outline however takes longer calculation time. The time basic applications utilize Carry Look-ahead plan (CLA) to infer quick outcomes yet they prompt increment in zone. Convey Select Adder is a bargain among RCA and CLA in term of region and deferral. Deferral of RCA is vast subsequently we have supplanted it with parallel prefix Adder which gives quick outcomes. In this paper, structures of 32-Bit Regular Linear Koggestone CSA, Modified Linear KS CSA, Regular Square Root (SQRT) KSA CSA and Modified SQRT KS CSA are outlined. Power and deferral of all these Adder structures are computed at various information voltages. The outcomes portray that Modified SQRT BK CSA is superior to anything the various Adder models as far as power however with little speed punishment.

Keywords: Brent Kung (BK) adder, Ripple Carry Adder (RCA), Regular Linear Brent Kung Carry Select Adder, Modified Linear BK Carry Select Adder, Regular Square Root (SQRT) BK CSA and Modified SQRT BK CSA, Regular Linear Koggestone Carry Select Adder, Modified Linear KS Carry Select Adder, Regular Square Root (SQRT) KS CSA and Modified SQRT KS CSA.

NOVEL ARCHITECTURE FOR OPTIMIZED IMPLEMENTATION OF BLOWFISH ALGORITHM FOR HIGH SECURITY APPLICATIONS

Pavan Kumar Reddy Atla — 2019-03-11

It is well-known that advanced encryption standard (AES) algorithm is used for protection against various classes of wireless attacks in wireless communication standard such as Wi-Fi, Wi-MAX, Zig-bee and Bluetooth. However, the AES is a complex algorithm that consumes a larger design core, time, and power source. Hence, this paper presents a development of an improved power-throughput Blowfish algorithm on Spartan 3E XC3S1200E field-programmable gate array (FPGA) as an alternative security algorithm. The proposed memory-based method is used to optimize the performance of Blowfish. The performance is analyzed in terms of its architecture, throughput, and power consumption.

Index Terms: advanced encryption standard, Blowfish, security, power-throughput, field-programmable gate array.