International Journal of Engineering Science and Generic Research http://ijesar.in/index.php/ijesar <p style="text-align: justify;">&nbsp;</p> <p style="text-align: justify;"><span style="font-family: lucida sans unicode,lucida grande,sans-serif;"><span style="font-size: 14px;"><strong>International Journal of Engineering Science and Generic Research (IJESAR) is a full-text database of OJS journal</strong></span></span></p> <p style="text-align: justify;"><span style="font-family: 'lucida sans unicode', 'lucida grande', sans-serif;">IJESAR is International publisher of academic and research journals; IJESAR publishes and develops titles in groups with the world's most prestigious learned societies and publishers. Our goal is to bring high quality research work</span></p> <p style="text-align: justify;"><span style="font-family: lucida sans unicode,lucida grande,sans-serif;"><span style="font-size: 14px;"><strong>Aims and Scope&nbsp;&nbsp;</strong></span></span></p> <p style="text-align: justify;"><span style="font-family: 'lucida sans unicode', 'lucida grande', sans-serif;">International&nbsp;Journal of Engineering Science and Generic Research&nbsp;(IJESAR) is an&nbsp;Open Access, international, multidisciplinary journals hub in the field multi disciplinary&nbsp;and will publish original research papers, short communications, invited reviews, Case studies and editorial commentary and news, Opinions &amp; Perspectives and Book Reviews written at the invitation of the Editor in following fields</span></p> <p style="text-align: justify;"><span style="font-family: lucida sans unicode,lucida grande,sans-serif;"><span style="font-size: 14px;"><strong>Important Notice&nbsp;&nbsp;</strong></span></span></p> <p style="text-align: justify;"><span style="font-family: 'lucida sans unicode', 'lucida grande', sans-serif;">Authors can now directly send their manuscript as an email attachment to editor@ijesar.in&nbsp;</span></p> <p style="text-align: justify;"><span style="font-family: lucida sans unicode,lucida grande,sans-serif;">All manuscripts are subject to rapid peer review. Those of high quality (not previously published and not under consideration for publication in another journal) will be published without delay. First-time users are required to register themselves as an author before making submissions by signing up the author registration form at journals website:&nbsp;</span><span style="font-size: 14px; font-family: 'lucida sans unicode', 'lucida grande', sans-serif;">www. http://ijesar.in</span></p> <p style="text-align: justify;"><span style="font-family: 'lucida sans unicode', 'lucida grande', sans-serif;">With the online journal management system that we are using, authors will be able to track manuscripts progress through the editorial process by logging in as author in authors Dashboard.</span></p> <p style="text-align: justify;"><span style="font-family: lucida sans unicode,lucida grande,sans-serif;"><span style="font-size: 14px;"><strong>Top Reasons for publication with us</strong></span></span></p> <p style="text-align: justify;"><strong style="font-family: 'lucida sans unicode', 'lucida grande', sans-serif;">Quick Quality Review:</strong><span style="font-family: 'lucida sans unicode', 'lucida grande', sans-serif;">&nbsp;The journal has strong international team of editors and reviewers, Rapid Decision and Publication</span></p> <p style="text-align: justify;"><strong style="font-family: 'lucida sans unicode', 'lucida grande', sans-serif;">Very Low Publication Fees:</strong><span style="font-family: 'lucida sans unicode', 'lucida grande', sans-serif;">&nbsp;Comparable journals charge a huge sum for each accepted manuscript. IJESAR only charge the fees necessary to recoup cost associated with running the journal</span></p> <p style="text-align: justify;"><strong style="font-family: 'lucida sans unicode', 'lucida grande', sans-serif;">Other features:</strong><span style="font-family: 'lucida sans unicode', 'lucida grande', sans-serif;">&nbsp;DIDS Assigned and Implemented the Open Review System (ORS).</span></p> Innovative Library en-US International Journal of Engineering Science and Generic Research 2456-043X <p><img style="border-width: 0;" src="http://i.creativecommons.org/l/by/4.0/88x31.png" alt="Creative Commons License" width="60" height="21" border="0"><strong>International Journal of Engineering Science and&nbsp;Generic Research (IJESAR)</strong><span style="line-height: 1.3em;">&nbsp;</span><span style="line-height: 1.3em;">by </span><span style="line-height: 1.3em;">Articles</span><span style="line-height: 1.3em;"> is licensed under a </span><a style="line-height: 1.3em;" title="Journal of Biomedical and Pharmaceutical Research" href="http://creativecommons.org/licenses/by/4.0/" target="_blank" rel="license noopener">Creative Commons Attribution 4.0 International License</a><span style="line-height: 1.3em;">.</span></p> UWB RECTANGULAR MICROSTRIP PATCH ANTENNAS WITH IMPROVED PERFORMANCE http://ijesar.in/index.php/ijesar/article/view/166 <p>This article presents ultra-wideband (UWB) rectangular microstrip antennas centered at 6GHz.&nbsp; For obtaining UWB, enhancement gain, a double layer microstrip antenna is proposed. The lower layer was etched by rectangular microstrip patch and two slots cutting in the metal ground plane. The patch acts as exciter and the slots as a radiator, and second layer as a cavity back. Impedance matching bandwidth achieved by tuning the length, width of slot, patches length, thickness of foam layer and tapered transmission length. The simulated result indicates good performance antennas, since it's achieved up to 89% bandwidth (active VSWR &lt; 2), high efficiency up to 0.9, and enhancement realized gain up to 9dB.</p> <p><strong>Index Term:</strong> UWB, Rectangular Patch, Slots, Cavity back, Reflection coefficient S11, and Gain</p> MostafaHassaneinHassanein Nagy Ali Mohamed Gomaa Mohamed AymanElsayedElsayed Haggag Saied Mohamed El-Saied Singy ##submission.copyrightStatement## http://creativecommons.org/licenses/by/4.0 2019-07-14 2019-07-14 5 4 10.32553/ijesar.v5i4.166 A NOVEL ARCHITECTURE FOR OPTIMIZED FIR FILTER BASED ON 16-BIT APPROXIMATE MULTIPLIER http://ijesar.in/index.php/ijesar/article/view/167 <p>FIR filter is valuable in numerous applications, for example, present day signal handling and correspondence frameworks. In this paper an enhanced FIR filter planned by utilizing 16X16 approximate multiplier dependent on parallel prefix adder is proposed. This proposed 16X16 approximate multiplier structured with four 8X8 approximate multipliers, three parallel prefix adder [PPA] and one OR gate. The parallel prefix adder give the less insertion delay, this prompts increment in the superior for the count in the less time. The 8X8 multiplier structured utilizing approximate tree compressor [ATC] and carry maskable adder [CMA]. The proposed multiplier is compared and a regular Wallace tree multiplier diminished basic way delay by 10%. This proposed multiplier improves the execution of the FIR filter. It is executed in Xilinx ISE version 14.7.</p> <p><strong><em>Keywords: </em></strong>Approximate multiplier, Parallel prefix adder, Brent-kung adder, FIR filter, Serial adder, incomplete adder cell.</p> M Narendra Reddy Er. Nuli Namassivaya ##submission.copyrightStatement## 2019-07-14 2019-07-14 5 4 DESIGN OF FIR FILTERS USING REVERSIBLE CIRCUITS http://ijesar.in/index.php/ijesar/article/view/168 <p>FIR filter is helpful in several applications such as modern signal processing and communication systems.&nbsp; In&nbsp; this&nbsp; paper&nbsp; a optimized&nbsp; FIR&nbsp; filter&nbsp; designed&nbsp; by using&nbsp; radix-4 multiplier based mostly&nbsp;&nbsp; on&nbsp; parallel&nbsp;&nbsp; prefix&nbsp;&nbsp; adder&nbsp;&nbsp; is proposed.&nbsp;&nbsp; This suggested&nbsp;&nbsp; radix-4 multiplier designed with brentkung adder.&nbsp; The parallel prefix adders provides the&nbsp; less insertion delay, this results in increase within the high performance for the calculation within the less time. . The planned radix-4 multiplier is compared&nbsp; with&nbsp; a typical vedic multiplier&nbsp; reduced critical&nbsp; path delay by V-day.&nbsp; This proposed multiplier improves the performance of the FIR filter. This Paper has been implemented in Xilinx ISE version 14.7.</p> <p>Keywords:&nbsp; Residue&nbsp;&nbsp;&nbsp; Number&nbsp;&nbsp;&nbsp; System&nbsp;&nbsp;&nbsp; (RNS); Reversible Circuits; Modular Adder; Parallel-Prefix Adder.</p> G SANDEEP KUMAR SMITHASHREE MOHAPATRA ##submission.copyrightStatement## http://creativecommons.org/licenses/by/4.0 2019-08-07 2019-08-07 5 4