International Journal of Engineering Science and Generic Research

UWB RECTANGULAR MICROSTRIP PATCH ANTENNAS WITH IMPROVED PERFORMANCE

MostafaHassaneinHassanein Nagy — 2019-07-14

This article presents ultra-wideband (UWB) rectangular microstrip antennas centered at 6GHz. For obtaining UWB, enhancement gain, a double layer microstrip antenna is proposed. The lower layer was etched by rectangular microstrip patch and two slots cutting in the metal ground plane. The patch acts as exciter and the slots as a radiator, and second layer as a cavity back. Impedance matching bandwidth achieved by tuning the length, width of slot, patches length, thickness of foam layer and tapered transmission length. The simulated result indicates good performance antennas, since it's achieved up to 89% bandwidth (active VSWR < 2), high efficiency up to 0.9, and enhancement realized gain up to 9dB.

Index Term: UWB, Rectangular Patch, Slots, Cavity back, Reflection coefficient S11, and Gain

A NOVEL ARCHITECTURE FOR OPTIMIZED FIR FILTER BASED ON 16-BIT APPROXIMATE MULTIPLIER

M Narendra Reddy — 2019-07-14

FIR filter is valuable in numerous applications, for example, present day signal handling and correspondence frameworks. In this paper an enhanced FIR filter planned by utilizing 16X16 approximate multiplier dependent on parallel prefix adder is proposed. This proposed 16X16 approximate multiplier structured with four 8X8 approximate multipliers, three parallel prefix adder [PPA] and one OR gate. The parallel prefix adder give the less insertion delay, this prompts increment in the superior for the count in the less time. The 8X8 multiplier structured utilizing approximate tree compressor [ATC] and carry maskable adder [CMA]. The proposed multiplier is compared and a regular Wallace tree multiplier diminished basic way delay by 10%. This proposed multiplier improves the execution of the FIR filter. It is executed in Xilinx ISE version 14.7.

Keywords: Approximate multiplier, Parallel prefix adder, Brent-kung adder, FIR filter, Serial adder, incomplete adder cell.

DESIGN OF FIR FILTERS USING REVERSIBLE CIRCUITS

G SANDEEP KUMAR — 2019-08-07

FIR filter is helpful in several applications such as modern signal processing and communication systems. In this paper a optimized FIR filter designed by using radix-4 multiplier based mostly on parallel prefix adder is proposed. This suggested radix-4 multiplier designed with brentkung adder. The parallel prefix adders provides the less insertion delay, this results in increase within the high performance for the calculation within the less time. . The planned radix-4 multiplier is compared with a typical vedic multiplier reduced critical path delay by V-day. This proposed multiplier improves the performance of the FIR filter. This Paper has been implemented in Xilinx ISE version 14.7.

Keywords: Residue Number System (RNS); Reversible Circuits; Modular Adder; Parallel-Prefix Adder.