Design of 128 bit Q-format multiplier by using Higher Radix Algorithm

Abstract

There has always been a quest going on for improving the performance of the multiplier as it is the key component in determining the performance of the digital signal processor. The Q-format multiplier implemented with Radix algorithm multiplier to be faster and area efficient and  for increasing the performance of the Q-format multiplier resulted in the outcome of this paper. This paper presents a novel method using Booth encoding towards generation of reduced number of partial products and redundant binary adder for adding these partial products for implementation of 128 bit Q-format signed multiplier which substantially improved the performance, area. This method has also been implemented for 64 bit multipliers along with 128 bit Q-format signed multiplier using Booth encoding and RB addition in Verilog targeted towards Xilinx FPGA Spartan3E and results compared with those obtained by using tool Xilinx 14.7

Keywords: Q-format: Booth encoding; Redundant binary adder; Xilinx; Verilog.