Fpga Implementation of High Performance Fully Pipelined Aes Algorithm Using Reversible Logic

Abstract

Advanced encryption standard (AES), a Federal Information Processing Standard (FIPS), and categorized as Computer Security Standard. The AES algorithm is a block cipher that can encrypt and decrypt digital information. It is capable of using cryptographic keys of 128.In this paper we have presented the FPGA based implementation of 128-bit Advanced Encryption Standard (AES) with fully pipelined architecture using Reversible Logic. Our proposed architecture can deliver higher throughput at both encryption and decryption operations. Xilinx ISE design suite 13.1 is used for design and Spartan-3E for implementation. Index Terms: Reversible logic, Advanced Encryption Standard